Are Clock and Reset Pins Required to Be Connected on All Blocks?

General Questions
1

I see that almost all blocks have Clock and Reset pins. Am I required to connect them? In most examples, they seem to be left floating.

2

The pins for Clock (CLK), Chip Enable (CE), Data Valid (DV), and Reset (RESET) are provided with default values, and in many cases, they do not need to be explicitly connected.

  • RESET: This pin is automatically connected to a synchronous signal aligned with the Clock Acquisition and pulses when the FPGA firmware is loaded. It ensures the block starts in a known state.

  • CLK (Clock): This is connected to the default clock of the board. Typically, this is the clock derived from the ADCs. For boards producing simple data (e.g., DT1260 or DT5771), the acquisition clock matches the sampling frequency. High-frequency boards such as V2730 (500 MHz) or DAQ121 (1 GHz) use a derived clock, typically at 1/4 of the sampling frequency.

  • CE (Chip Enable) and DV (Data Valid): If these pins are not connected, they are forced to logic 1 by default. This means that the blocks will always treat the data as valid and remain active.

Thus, if the default behavior works for your application, you do not need to explicitly connect these pins in your design. However, if you require custom control, you can connect them to manage when the blocks are active or when data is considered valid.