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About the General Questions category
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0
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19
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September 5, 2024
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Readign DT1260 wo sci-compiler
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1
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57
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November 18, 2025
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Local compilation for VX2730
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2
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103
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October 29, 2024
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Can I Use Newer Versions of Xilinx Vivado or Intel Quartus for Compilation Than Those Specified for the Boards?
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1
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130
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October 12, 2024
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What Are the Default Clock Frequencies for Various Boards?
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1
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100
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October 12, 2024
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Improving Schematic Visibility in SciCompiler
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2
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87
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October 12, 2024
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What Is the Main Difference Between LabVIEW and Sci-Compiler?
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1
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69
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October 12, 2024
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Why Can't I Simply Use Double Precision Floating Point Like in C Instead of Fixed Point in FPGA Designs?
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1
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85
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October 12, 2024
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Placing Registers and Oscilloscopes in Sub-Designs
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1
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75
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October 12, 2024
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Real-Time Debugging of a Signal Processing Algorithm
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1
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64
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October 12, 2024
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Measuring the Duration of a Digital Pulse from LEMO on V2495 and Reading It with a Register
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1
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85
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October 12, 2024
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Are Clock and Reset Pins Required to Be Connected on All Blocks?
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1
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67
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October 12, 2024
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Oscilloscope Dual and Resource Explorer Compatibility Issues
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1
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94
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October 12, 2024
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Clarification on Scaler Functionality and New Updates
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1
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69
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October 12, 2024
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Data Merger Block Missing from DAQ Menu
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1
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71
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October 12, 2024
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Bit-Vector Register File Readback Issue in Resource Explorer
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1
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59
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October 12, 2024
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Changing the Type of a Schematic Input or Output Port in a Sub-design
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1
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75
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October 12, 2024
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How does SciCompiler handle hierarchical designs, and what role do sub-designs play in them?
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1
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63
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October 12, 2024
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How to use V2495 board with SciSDK?
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1
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63
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October 12, 2024
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Resource explorer
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1
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98
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October 9, 2024
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